Wireline Transceivers
Developing PPA optimized NRZ and PAM4 SerDes transceiver core for backplane wireline communication standards
RF Wireless Communication
Developing Quad-Transceiver Beamformer IC having 6-bit Phase-Control and 6-bit Gain Control
Automotive SERDES
Developing asymmetrical, high-performance SerDes Cores for in-vehicle connectivity for ASA Motion Link and broadband connection of sensors for autonomous driving
D2D and SiP Subsystem
Developing High-Performance D2D PHY for Protocol and Interface-agnostic and standard UCIe standards for chiplet connectivity for AI/ML, cloud computing
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