PLL-IP Overview
PLL-IP Overview
Fermionic Design offers wide portfolio of PPA optimized SERDES IPs, wide-range PLLs and Analog-Glue IPs in various nodes. Fermionic Design IPs are highly programmable, developed using robust design flow and comes with after-sales integration support as well as documentation.
Our PLLs product-line includes:
- Fractional-N PLL core: Programmable
- general purpose frequency synthesizers.
- Jitter performance meeting common wireline communication standards such as PCIe Gen5/Gen4/Gen3, USB4.0
- Supports Spread spectrum modulation
- Integrated 24-bit delta-sigma modulator: Frequency resolution < 0.1ppm
- Optional support for Xtal interface
- Zero-Delay-Buffer PLL Cores for Multi-node Clock-distribution
- ZDB-PLL core supporting spread-spectrum tracking