Silicon IP Portfolio
Silicon IP Portfolio
Fermionic Design offers wide portfolio of PPA optimized SERDES IPs, wide-range PLLs and Analog-Glue IPs in various nodes. Fermionic Design IPs are highly programmable, developed using robust design flow and comes with after-sales integration support as well as documentation.
- Architecture Supports up to PCIe Gen5 (32Gbps) data-rate
- Soft RTL for SERDES PIPE PCS
- Supports multi-protocol USB4.0, PCIe Gen1/2/3/4/5, JESD204A/B/C
- Integrated TX PLL
- Programmable TX-FFE
- Architecture suitable for low-latency application
- Programmable CTLE and adaptive 7-Tap DFE
- Non-destructive Eye-monitor
- PRBS Generator and checker